Description
octal D-type Edge Triggered Flip-Flop with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. This device is particularly attractive for implementing buffer registers and I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock and the Q outputs are set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the S374 device simplify system design as AC and DC noise rejection is improved by typically 400mV due to the input hysteresis. A buffered output-control input can be used to place the eight outputs in either a normal logic state or the high-impedance state.Full parallel access for loading
Buffered control inputs
Clock-enable input has hysteresis to improve noise rejection
PNP Inputs reduce DC loading on data lines
Pb-free product
Applications
Clock & Timing, Communications & Networking
